A typical prior art system is shown in FIG. 1. An analog input signal such as sound signal is fed from a line 1 and is converted into a digital value in an analog/digital converter circuit 2, and is applied to a processor 3 for data processing. The digital signal processed in this processor 3 is sent to a digital/analog converter circuit 4 to be converted into an analog signal, and is output from a line 5 to drive, for example, a speaker. A microcomputer 6 is connected to the processor 3. The arithmetic processing speed of the processor 3 is faster than that of the microcomputer 6. To transfer the data from the microcomputer 6 into the processor 3, the data from the microcomputer 6 is stored in series in a receiving register 8 by way of a line 7.
In this way the data from the microcomputer 6 is transferred until the receiving register 8 is filled up, when a flag Fl is set up on a line 9, and is applied to a control circuit 10. The content of the receiving register 8 is stored in a memory 11. The control circuit 10 generates, when the flag Fl is set up, a signal for temporarily stopping transmission of the data from the microcomputer 6 through a line 14. After the content of the receiving register 8 is stored in the memory 11, a signal indicative of this storing is given to the microcomputer 6 from the control circuit 10, and the microcomputer 6 outputs the remaining data from the line 7 to the receiving register 8. Thus the content in the receiving register 8 is further stored in the memory 11 as mentioned above.
The control circuit 10 repeats operations in every specified sampling period W shown in FIG. 2 (1). In this sampling period W, digital signal processing is conducted in period W1 shown in FIG. 2 (2), and in the remaining period W2 shown in FIG. 2 (3) the data from the microcomputer 6 is stored in the memory 11 by way of receiving register 8.
In such a prior art system, if the period W1 for digital signal processing in the processor 3 is relatively long, the period W2 for transferring the data from the microcomputer 6 to the processor 3 becomes relatively short. Therefore, in order to transfer the data from the microcomputer 6 to the processor 3 securely, the sampling period W must be set sufficiently long. On the other hand, with each sampling period W, it is sometimes not necessary to transfer data from the microcomputer 6 to the processor 3, and in such a case no processing of the processor 3 is carried out in the remaining period W3 (see FIG. 2 (3)), and the time is thus wasted. In the prior art, since the data is transferred by program processing in this way, the period W1 for digital signal processing allowed in each sampling period W may become short, or it may be necessary to prolong the sampling period W, so that the quality of signal processing may deteriorate.
Likewise, when transferring data from the processor 3 to the microcomputer 6, the content of the memory 11 is stored in the transmitting register 12, and the content of this transmitting register 12 is transferred to the microcomputer 6 by way of a line 13. If there is much content to be transmitted, when the data is set in the transmitting register 12, a signal indicative of this is given to the control circuit 10 through a line 15, and a flag F2 is set up. The control circuit 10 outputs a signal to express the setting of the content in the transmitting register 12 to the microcomputer 6 through a line 14, so that the microcomputer 6 can accurately receive the content of the transmitting register 12. In such data transfer from the processor 3 to the microcomputer 6, a same operation as in the operation described in relation to FIG. 2 is effected, and the period W1 of digital signal processing that can be carried out in each sampling period W may be short, or it is necessary to elongate the sampling period W, which results in a deterioration of the quality of signal processing.
It is hence a primary object of the invention to present an apparatus and system for data transfer capable of increasing the time for digital signal processing, by transferring data between a controlling unit and processing unit mutually at high speed, eliminating wasted time, and capable of simplifying the constitution while shortening the transfer time of data.
It is other object of the invention to present an apparatus and system for data transfer capable of reducing the data length for transfer while significantly increasing the data transfer speed.